As the operating voltages for CMOS transistor circuits have decreased, variations in the threshold voltages for the transistors have become more significant. Although low operating voltages offer the potential for reduced power consumption, threshold voltage variations due to process and environmental variables often prevent optimum efficiency and performance from being achieved due to increased leakage currents.
Threshold voltage variations may be compensated for by body biasing. In typical CMOS transistors, the body of the transistor is connected to a supply rail (e.g., Vss for NMOS, and Vdd for PMOS). In this configuration the transistor is often treated as a three terminal device.
Body biasing introduces a reverse bias potential between the bulk and the source of the transistor that allows the threshold voltage of the transistor to be adjusted electrically. The purpose of body biasing is to compensate for: 1) process variations; 2) temperature variations; 3) supply voltage variations; 4) changes in frequency of operation; and 5) changing levels of switching activity.
Whereas the typical CMOS transistor is a three-terminal device, the body biased CMOS transistor is a four-terminal device, and thus requires a more complex interconnect scheme. Connections for body biasing may be made on the substrate surface using conventional metal/dielectric interconnects similar to those used for typical gate, drain, and source connections, or they may be made using buried complementary well structures (e.g., buried N-well).
Prior Art FIG. 1 shows a conventional CMOS inverter 100. A P-type substrate 105 supports an NFET 110 and a PFET 120. The NFET 110 comprises a gate 112, source 113, and drain 114. The PFET 120 resides in an n-well 115, and comprises a gate 122, drain 123, and a source 124. Body bias can provided to the PFET 120 through a direct bias contact 135a, or by a buried n-well 125 using contact 135b. Similarly, body bias may be provided to the NFET 110 by a surface contact 140a, or by a backside contact 140b. An aperture 130 is provided in the buried n-well 125 so that the bias potential reaches the NFET 110. In general, a PFET 120 or an NFET 110 will be biased by one of the alternative contacts shown.
In a complex integrated circuit different parts of the circuit may require different bias voltages, and a given part of the circuit may also require a variable bias. A variable bias is particularly desirable when minimum power dissipation is required in a circuit.